CMOS FETs are useful as semiconductor switches operating at widely ranging supply voltages with low power consumption. According to conventional techniques, they are produced in a silicon substrate of one conductivity type (e.g. n) a region of which is subjected to implantation of impurities of the opposite conductivity type (p) to form a so-called well serving as the site of one of the two complementary FETs, specifically of the n-channel FET in the case of a p-well. An adjoining region of the original conductivity type then becomes the site of the other FET.
It is, of course, desirable that the two FETs be spaced as closely as possible from one another and from other components of the same silicon wafer. In order to avoid undesirable interaction between such closely spaced components, which could appear with operations at a relatively high voltage, it is known to separate them from one another by barriers which may be in the shape of surrounding guard rings and which in the case of field-effect transistors are referred to as channel stops. These channel stops are generally of the same conductivity type as the adjoining substrate region carrying the protected FET, but with a higher impurity concentration.
According to a method described in PRINCIPES ET APPLICATIONS DES CI/MOS, by H. Lilen, published 1972 by Editions Radio in Paris, France, pages 54-59, channel stops of p+ conductivity for an n-channel MOSFET are formed in a p-well of an n-type silicon substrate simultaneously with source and drain zones of a p-channel MOSFET in an adjoining region whereupon channel stops of n+ conductivity are formed in that adjoining region simultaneously with source and drain zones in the p-well; see particularly FIGS. 3-12 on page 57. The unavoidable physical separation of the n+ and p+ channel stops produced by this technique limits the number of semiconductor components that can be accommodated on a silicon wafer of given dimensions. To achieve a higher component density, U.S. Pat. No. 4,013,484 describes a process in which these channel stops of opposite conductivity type can be made contiguous. According to the latter process, two patches of silicon nitride topped by silicon oxide are deposited on a layer of silicon oxide overlying the n-type substrate above spaced-apart regions destined to become an n-channel FET and a p-channel FET, respectively. A heavy layer of field oxide is then produced in areas not covered by the two patches and is thereafter partly removed in a zone immediately adjoining the first patch to facilitate the implantation of p-type impurities (boron) into that zone, this being followed by a drive-in cycle in which the substrate is heated to promote the diffusion of the implanted boron into the region underlying that first patch to form a p-well. Thereafter, additional boron impurities are implanted at a reduced energy level to intensify the impurity concentration in the marginal zone of the p-well, thereby forming the channel stop associated with the n-channel FET. The formation of the other channel stop by the implantation of n-type impurities (arsenic) in a zone immediately adjoining the second patch, overlain by a remaining portion of the partly removed field oxide, is carried out upon removal of that remaining layer portion but could also have been performed at an earlier stage, before the thickening of the oxide layer; in that instance, as likewise noted in the patent, an arsenic-doped substrate portion adjoining the first patch would have to be removed before implantation of the boron particles or else the concentration and the penetration depth of these particles would have to be increased to compensate for the presence of the added n-type impurities. In any event, the prior process requires the buildup of another heavy oxide layer in the previously stripped zones of the substrate in which the two channel stops are formed, thereby creating an insulating barrier between the two complementary MOSFETs. It is only after this second oxidation step that the patches overlying the two MOSFET regions are removed to expose their respective source and drain sections for doping with impurities of the proper conductivity types.
The formation of an oxide layer of considerable thickness (on the order of 10,000 A), occurring at the expense of an underlying silicon substrate, is a lengthy procedure requiring the maintenance of that substrate at a high temperature for a period of roughly 12 hours. Such a protracted heat treatment may have detrimental effects upon the substrate which are cumulative if the operation is repeated.